The present invention relates to a semiconductor device, and more particular, to a semiconductor memory device with a delay locked loop circuit.
A semiconductor memory device embodied in a system which includes a plurality of semiconductor devices is used for storing data. The semiconductor memory device outputs data stored in cells corresponding to an address outputted from a data requesting unit such as a central processing unit or stores data provided from the data requesting unit into the cells.
As the operational speed of systems including a plurality of semiconductor devices has increased and technology related with a semiconductor integrated circuitry has advanced, there has been a demand for increased data access speed from semiconductor memory devices. In order to access data from a semiconductor memory device at high speed, a synchronous memory device which receives a clock and can access data of each cycle of a received clock has been proposed. Nevertheless, such a synchronous memory device does not meet the data access speeds demanded by modern systems, particularly the data requesting unit included in the system. In response, a double data rate (DDR) synchronous semiconductor memory device has been proposed which can access data on both the rising and falling edges of a clock.
The DDR synchronous semiconductor memory device should receive or output two items of data within one cycle of a clock, since the DDR synchronous semiconductor memory device accesses one item of data for every transition of the clock. That is, the DDR synchronous semiconductor memory device should output or receive data exactly synchronized with the rising edge and falling edge of the clock. Typically, the output circuit of the DDR synchronous semiconductor memory device receives the system clock through a clock transfer path including a clock buffer, clock transmission lines, and the like inside the DDR synchronous semiconductor memory device and outputs data synchronized with the received clock.
However, the clock reaches the output circuit of the DDR synchronous semiconductor memory device with an essential delay which occurs while passing through the clock input buffer and the clock signal transmission lines in the DDR synchronous semiconductor memory device. Although the output circuit outputs data in synchronization with the internally received clock, data is delayed by the essential delay, and are provided from the DDR synchronous semiconductor memory device out of phase with the received clock used by an external device receiving the data.
To solve the problem described above, the DDR synchronous semiconductor memory device includes a circuit, i.e., a delay locked loop circuit, for adjusting the essential delay by locking a delay of the transferred clock. The delay locked loop compensates for a delay introduced by the clock transfer path of the semiconductor memory device. The delay locked loop circuit detects a delay which occurs while an input clock passes through the clock transfer path including the clock input circuit, the clock signal transmission lines, and the like, and delays the input clock for a delay time corresponding to the detected delay value to thereby provide a delay locked clock to the output circuit. That is, the delay locked loop circuit intentionally delays and locks the input clock by a constant delay value depending on an amount of detected delay to provide the delay locked clock to the output circuit. Then, the output circuit outputs data synchronized with the delay locked clock. Then the data output from the output circuit is transferred to the external devicein synchronicity with the input clock.
However, as the frequency of the input clock increases more and more, the operating margin for accessing data becomes much shorter. At higher frequencies, it is more important to assure that the delay locked clock has a 50% duty cycle. If the duty cycle of the delay locked clock is not 50%, the data processing margin of either the rising edge or the falling edge of the delay locked clock becomes too short for proper operation. Therefore, recent DDR synchronous semiconductor memory devices have a duty cycle correction circuit for correcting the duty cycle of a delay locked clock generated by a delay locked loop circuit.
FIG. 1 shows a block diagram of a conventional semiconductor memory device. The conventional semiconductor memory device includes a clock buffer 10, a delay locked loop circuit 20, a duty correction unit 30, a clock transfer unit 40, a data output unit 50 and a controlling unit 60.
The clock buffer 10 receives clocks ECLK and ECLKB to output to an internal clock ICLK0. The delay locked loop circuit 20 receives the internal clock ICLK0 to generate a delay locked clock ICLK1. The delay locked clock ICLK1 is a reference clock for the output of data synchronized with the clocks ECLK and ECLKB. The duty correction unit 30 corrects the duty cycle of the delay locked clock ICLK1 to generate an internal clock ICLK2. The clock transfer unit 40 receives the internal clock ICLK2 to generate internal clocks ICLK3 and ICLK3B in response to a control signal CN. The data output unit outputs data D[0:N-1] provided from a memory core area in response to the internal clocks ICLK3 and ICLK3B. The controlling unit 60 generates the control signal CN which is used for controlling an operation of the clock transfer unit 40. The control signal CN has information corresponding to a read latency and a burst length determined by an operation mode of the conventional semiconductor memory device. The read latency specifies a period between the input timing of the read command and the output timing of corresponding data. The burst length means the number of output data items corresponding to a command.
FIG. 2 shows a waveform diagram representing operation of the conventional semiconductor memory device shown in FIG. 1. The conventional semiconductor memory device receives the clocks ECLK and ECLKB to generate the internal clocks ICLK3 and ICLK3B as reference clocks for the data output unit 50 to output data. Consequently, the data output unit outputs data synchronized with the internal clocks ICLK3 and ICLK3B.
When the duty cycle of the internal clocks ICLK3 and ICLK3B is 50%, the data output unit 50 has the maximum margin to output data on every transition of the internal clocks ICLK3 and ICLK3B. If the duty cycle of the internal clocks ICLK3 and ICLK3B is not 50%, the data processing margin for either the rising edge or the falling edge of the internal clocks ICLK3 and ICLK3B is reduced.
Although the duty correction unit 30 corrects the internal clock ICLK1 to generate the internal clock ICLK2 with a duty cycle of 50%, the duty cycle of the internal clocks ICLK3 and ICLK3B can become different. Then, the data output unit 50 can not carry out data output operations for a predetermined equal time on every transition of the internal clocks ICLK3 and ICLK3B.
In the situation that the frequency of the clock input to the semiconductor memory device becomes higher and higher, if the data output unit 50 attempts data output operations using reference clocks of which the duty cycle is not substantially 50%, the data output unit may not have a sufficient data processing margin for output of data. The data output unit may not even be able output data an each predetermined transition time of a clock.